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Altera_Forum's avatar
Altera_Forum
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17 years ago

multiplexer synthesis

Hi to all,

I am new to the forum. I have a question about multiplexers.

Our design is in VHDL and there are many cases when depending on a value of a register I have to multiplex different values onto a bus. For example

case MYREG is

when REGVAL_1 | REGVAL_2 =>

A <= B;

when REGVAL_3 | REGVAL_4 | REGVAL_5 | REGVAL_6 | REGVAL_7 | REGVAL_8 | REGVAL_9 =>

A <= (others => '0');

when others =>

A <= (others => '-');

end case;

MYREG can have 9 defined values and therefore it is stored on 4 bits. After synhtesis, I can see in RTL viewer that there are 16:1 multiplexers (on each bit of the bus). On the other hand the code suggests that I would need only a 2:1 mux. Is there a way to tell quartus not to have always a full decoding of the register value? I suppose that would require less resource/routing. Thanks for your reply.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    If your values are fixed then try some manual checks at bits and mux accordingly.

    Also note you don't need second line, just use when others.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    Yes, my values are fixed. Indeed I could do it manually, optimize out the decoding logic.

    However, is there an automatic way / setting for that?

    I've also read the coding style section in the quartus handbook. It says that if I put don't care values for the unused states I get improvement in resource usage which just did not happen in my case.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Be careful of relying on the RTL viewer too much. It's just supposed to represent what your code is before synthesis. There's a good chance synthesis will combine all of the conditions and end up giving you a 2:1 mux. You can use the technology map viewer(admittedly much more difficult to read), or put it in a lone project and look at how much logic it uses.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    The advantage of a "don't care" is to let compiler choose but it adds one more test. So remove it and see.

    I don't think current quartus is friendly enough to do those bit DIY jobs
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    And actually you have a 3:1 mux. Your when others => 0, is a valid condition unless the synthesizer can obviously tell that REGVAL will always have one active state, which I doubt is the case. So if they're all disabled, then the output is 0. Just make it when others for the second condition if there are really only two conditions you want.