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Just add more than one state machine.
Quartus seems to recognise any case statement which changes a register between different entries as a state machine. I call all my state machines things like "stateMachine", "mgmtStateMachine", etc.
It helps to use (in Verilog at least) localparam definitions for each of your states.
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I found that unless each state machine follows very specific rules, they won't show up. It is also possible that you're missing something, for example using a blocking assignment instead of a non-blocking in a single state, that is causing issues. Getting the syntax correct can cause a headache for the viewer. I'd double-check that first.
I have several modules with 3+ state machines, so it has to be something else. I write mine differently (all synchronous), but it works either way.
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