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please paste the error here
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OK， the down is my code for clkctrl_cs
clkctrl_cs clkctrl_cs1(.clkselect(spll1) ,.inclk0x(clk0_100) ,
.inclk1x(clk125_0) ,.outclk(clk0)) ;
...............
clkctrl_cs clkctrl_cs8(.clkselect(spll1) ,.inclk0x(clk315_100) ,.inclk1x(clk125_315) ,.outclk(clk315)) ;
and the down is the error
Error: inclk port of Clock Control Block
Error: inclk port of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs4|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be driven by 1 PLLs but is driven by 2 PLLs
Info: Clock Control Block is driven by PLL "dso_pll:ll_inst|pll1:ll1_inst|altpll:altpll_component|pll1_altpll:auto_generated|pll1"
Info: Clock Control Block is driven by PLL "dso_pll:ll_inst|pll0:ll0_inst|altpll:altpll_component|altpll_km93:auto_generated|pll1"
Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs5|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used
Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs6|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used
Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs7|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used
Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs8|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used
Error: Quartus II Partition Merge was unsuccessful. 8 errors, 0 warnings
Error: Peak virtual memory: 208 megabytes
Error: Processing ended: Wed Nov 02 17:43:24 2011
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:04
Error: Quartus II Full Compilation was unsuccessful. 10 errors, 54 warnings
thank you very much
Honored Contributor
