Multiple clock problem ？

i am sorry disturb you again , but i have a quartus about multiple CLOCK ,can you have a suggest to solve it ，

i use EP3C5,and it only have two PLLS. and the soft is quaruts10.0

here is my code :

module dso_pll(clkin0,clkin1,clr,

ad_clk0,ad_clk180,ad_clk90,ad_clk270,

ad_clk45,ad_clk135,ad_clk225,ad_clk315,

clk0,clk180,clk90,clk270,

spll1,

clk45,clk135,clk225,clk315);

input clkin0,clkin1,spll1;

output ad_clk0,ad_clk180,ad_clk90,ad_clk270; // clk for ad//

output clk0,clk180,clk90,clk270,clk100b;/// sample for AD///

output ad_clk45,ad_clk135,ad_clk225,ad_clk315;// clk for ad//

output clk45,clk135,clk225,clk315;/// sample for AD9288/

wire clk0,clk45,clk90,clk135,clk180,clk225,clk315,clk270;

wire ad_clk0,ad_clk180,ad_clk90,ad_clk270;

wire ad_clk45,ad_clk135,ad_clk225,ad_clk315;

wire clk125_0,clk125_45,clk125_90,clk125_135,

clk0_100,clk45_100,clk90_100,clk135_100;

pll0 pll0_inst(.inclk0(clkin0),

.c0(clk125_0),.c1(clk125_45), ///125m

.c2(clk125_90),.c3(clk125_135));

pll1 pll1_inst(.inclk0(clkin1),.c0(clk0_100),.c1(clk45_100),

.c2(clk90_100),.c3(clk135_100));//100m

assign ad_clk0 = clk0 ;

assign ad_clk90 = clk90 ;

assign ad_clk180 = clk180 ;

assign ad_clk270 = clk270 ;

assign ad_clk45 = clk45 ;

assign ad_clk225 = clk225 ;

assign ad_clk135 = clk135 ;

assign ad_clk315 = clk315 ;

assign clk0 = spll1 ? clk125_0 : clk0_100;

assign clk45 = spll1 ? clk125_45 : clk45_100;

assign clk90 = spll1 ? clk125_90 : clk90_100;

assign clk135 = spll1 ? clk125_135 : clk135_100;

assign clk180 = spll1 ? (!clk125_0) : (!clk0_100);

assign clk225 = spll1 ? (!clk125_45) : (!clk45_100);

assign clk270 = spll1 ? (!clk125_90) : (!clk90_100);

assign clk315 = spll1 ? (!clk125_135) : (!clk135_100);

endmodule

:: clk0 .clk45,clk90,clk135,clk180,clk225,clk270,clk315 is used for FPGA which is used to sample for Ad_data.

:: AD_CLK0,AD_CLK45,AD_CLK90,AD_CLK135,AD_CLK225,AD_CLK270.AD_CLK315

is provided for AD

:: the clk125_0 is 125M and phase is 0,

:: the clk125_45 is 125M and phase is 45,

:: the clk125_90 is 125M and phase is 90,

:: the clk125_135 is 125M and phase is135,

:: the clk125_180 is 125M and phase is 180,

:: the clk125_225 is 125M and phase is 225,

:: the clk125_270 is 125M and phase is 270,

:: the clk125_315 is 125M and phase is 315,

such as clk0_100 , but clk0_100 is 100M .

then i have a quartus is that

1 ： how i make sure that Length of time form ad_clk0 to outpin ,and from ad_clk90 to output pin , ... is equivalent。

2 : when the clk is 125M, and i make the PLL0 phase is "0,45,90,135 " ,but i measure the ADCLK output pin ,then i find that

ad_clk0 -> ad_clk45 : 1050ps ,

ad_clk45 -> ad_clk90 : 500ps .

........

then i have quartus that how i can make sure the length of time is equivalent .

thank you very much