multicycle path for relaxing design

Hello,

I want to use a multicycle path timing constraint (Synopsys Design Constraint), which relaxes the setup and hold relationships between a pseudo domain clock crossing. I use divided clocks. The operations which are clocked by a slower clock will have more available time so there will be no more critical paths in this operations.

Question:

Is Quartus or other Tools able to reduce the area of such multicycle designs?

Or did I forget something in the SDC file or in Quartus or did I wrote wrong code?

Does the multicycle constraint have any effects on the synthesis?

"Synplifiy says": "It is important to specify which paths are multicycle to avoid having the Quartus II and the Synplify compilers work excessively on a non-critical path. "

I'm wondering If the compilers are intelligent enough to serialize complex parallel operations in the "multicycle process" for shrinking area requirements or for sharing the ressources.

Example:

If I specify a SDC file with a multicycle path constraint I recognized no differences between the synthesis of the following code towards the version without the constraint.

set_multicycle_path -setup -end -from [get_clocks {clk80}] -to [get_registers {relaxed_component:rlx_cmp|result[0] ... ... relaxed_component:rlx_cmp|result[29] relaxed_component:rlx_cmp|result[30]}] 10

entity relaxed_component is 
	port (
                ...
	operand_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	operand_2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	...
	result    : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
    );
end entity relaxed_component ;
architecture ....
op:process(clk, reset)
type states is (idle, compute);
variable state      : states;
variable a, b, c, d, e, f, g, h, i : signed(15 downto 0);
begin
if (reset = '1') then
	a := X"0000";
	b := X"0000";
	c := X"0000";
	d := X"0000";
	e := X"0000";
	f := X"0000";
	g := X"0000";
	h := X"0000";
	i := X"0000";
	ack <= '0';
	result <= X"00000000";
	state := idle;
elsif (clk80'event and clk80 ='1') then
	if (ena = '1') then
		ack <= '0';
		case state is
		when idle =>
			if (req = '1') then
				state := compute;
				result <= X"00000000";
			end if; 
		when compute =>
				a := signed(operand_1);
				b := signed(operand_2);
				c := signed(operand_1) + signed(operand_2);
				d := signed(operand_1) - signed(operand_2);
				e := signed(operand_1) mod signed(operand_2);
				f := signed(operand_2) mod signed(operand_1);
				g := signed(operand_1) / signed(operand_2);
				h := signed(operand_1(7 downto 0)) * signed(operand_2(7 downto 0));
				i := signed(operand_1) and signed(operand_2);
				a := i;
				b := h;
				c := g + f;
				d := e - d;
				e := c mod b;
				f := a mod i;
				g := h / a;
				h := g(7 downto 0) * e(7 downto 0);
				i := d and c;
				a := b;
				b := a;
				c := i + h;
				d := g - f;
				e := e mod d;
				f := c mod a;
				g := i / h;
				h := g(7 downto 0) * f(7 downto 0);
				i := e and d;
				a := c;
				b := h;
				c := b + a;
				d := h - i;
				e := g mod f;
				f := e mod d;
				g := c / b;
				h := g(7 downto 0) * a(7 downto 0);
				i := d and c;
				result <= std_logic_vector((a and b) + (c or d) + (e or f) - (g mod h) * i);
				state := idle;
				ack <= '1';
		end case;
	--end if;
end if;
end process;
end behavior;

I'm searching for Literature about design of components with divided clocks. The communication between the components isn't as easy as I thought.

TIA

Axel