Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

mSGDMA: Incorrect operation but the behavior changes when SignalTapII is inserted.

Hi all, Please help me. I am using two mSGDMA modules to read and write DDR3 on DE5-NET board with quartus ii ver 14.1.1. The mSGDMA is of the modules of Qsys ver 14.1. The problem that ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

It seems to me that I have the same issue. I’m using the mSGDMA core in a simple PCIe -> mSGDMA -> Avalon-ST DC FIFO qsys system (Quartus v14.0.2). The mSGDMA core is configured in MM to Stream mode (parameters are shown in the attachments). The mSGDMA core stalls with the busy flag asserted at random lengths of bytes: 

. . .
Transferring 97517568 bytes ... 
Transferring 98566144 bytes ... 
Transferring 99614720 bytes ... 
Transferring 100663296 bytes ... 
Transferring 101711872 bytes ... 
Transferring 102760448 bytes ... 
Transferring 103809024 bytes ... 
Transferring 104857600 bytes ... 
Transferring 105906176 bytes ... 
Transferring 106954752 bytes ... 
Transferring 108003328 bytes ... 
Transferring 109051904 bytes ... 
Transferring 110100480 bytes ... 
Transferring 111149056 bytes ... 
Transferring 112197632 bytes ... 
Transferring 113246208 bytes ... 
Transferring 114294784 bytes ... 
Transferring 115343360 bytes ... 
Transferring 116391936 bytes ... 
Transferring 117440512 bytes ... <--- indefinitely

I have also tried with the last version of mSGDMA core from Altera Wiki, but the result is the same. Can you plz provide your fifo_with_byteenables?