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BS11's avatar
BS11
Icon for New Contributor rankNew Contributor
3 years ago

Moving pin on PCIe HARD IP to another location

Hi, I am trying to move the pin location of the channel 0 RX/TX to a different location. They are both in the PCIE HARD IP pin designations. I see the following error below but cannot find any c...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.


Thank you for your patience.


Best regards,

Wincent_C_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    1. Why would you reassign the pin location? is there any specific reason for doing that?
    2. Is the design able to run well before you change the pin location?

    Can you please check the IO pins and clock is compact to the Stratix V IO user guidelines.

    And also check by mistake using the transceiver pins. If using the transceiver pins , the above error might possible occur.

    Regards,

    Wincent_C_Intel

    • BS11's avatar
      BS11
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      The design has no problem compiling in it’s original form. We have a box from an old design where the pins need to be reassigned to work with the connectors. I am trying to prove a few things:

      1. We can reassign pins between different channels in the PCIe HARD IP. It seems that we should be able to do so.

      Once I can establish that 1 is possible then I will attempt 2 below:

      1. Reassign the hip serial TX/RX pins to a non-PCIE HARD IP location to see if I can compile the design. I am attempting this to prove whether this is possible due to the previous design.

      Your Question: And also check by mistake using the transceiver pins. If using the transceiver pins , the above error might possible occur.

      I’ve checked the transceiver pins and am reassigning to the pins in GXB_TX_L10 from GXB_TX_L0 for the 5SGXMA4K3F40C3 part. These pin locations should be correct. Locations are taken directly from Pin planner PCIe HARD IP diagram for the part listed(shown under heading “Pin Location” on spreadsheet snip below).

      Remapping in Assignment Editor:

      hip_serial_tx_out0 --- AU37 Reassigned to U37

      hip_serial_tx_out0(n) --- AU36 Reassigned to U36

      hip_serial_rx_in0 --- AV38 Reassigned to V38

      hip_serial_rx_in0(n) --- AV39 Reassigned to V39

      Your Question: Can you please check the IO pins and clock is compact to the Stratix V IO user guidelines.

      Not sure what you’re asking here. Can you please restate your question?

      Thanks,

      Bryan