Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Module Instantiation Problem

I have two modules in separate files sub.v and test1.v as shown below. When I attempt to compile them I get the following error messages. ** Error: C:/Users/User/Documents/UCLA/Senior(2015-201...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello,

Instance of 'SUB' module needs to be outside initial block. Also variable c in 'TEST1' module needs to be declared as 'wire' since it is output of 'SUB' module.

Something like,

module TEST1;

reg [31:0] a,b;

wire [31:0] c;

initial begin

a = 12;

b = 9;

end

SUB s(a,b,c);

endmodule

Cheers,

Bhaumik