Altera_Forum
Honored Contributor
14 years agomodlesim 6.6d
i am new to modlesim, i downloaded the latest version, i hope if someone tells me how to simulate vhdl program with modlesim in simple way
i am new to modlesim, i downloaded the latest version, i hope if someone tells me how to simulate vhdl program with modlesim in simple way
I suggest you ask more specific questions. You can write the testbench in quartus but you cannot compile it in there.
i think there is a way where we can force some inputs and see the outputs in modlesim
No there is not.
The old quartus simulator allowed that, but that is not included in Quartus 10+i can see it in modlesim after selecting new source , but do i need to write all the possible inputs
I suggest you focus your questions more clearly - it is not very clear what you are talking about.
my question is, as i have VHDL codes that are working fine and i simulated then in quartus ii, and i used the waveform file in quartus , it works fine
i want to use modlesim to simulate the same vhdl code(program), so as i did in quartus i selected some values to the inputs and observed the output response.. is there a way i do the same in modlesim, putting some input values and see the outputs,Like I said, the old quartus simulator supports what you are trying to do. You may be able to export this as a file Modelsim can understand, but usually you create another VHDL file as the testbench for modelsim.
If you think they are working fine using the quartus simulator, why do you want to use modelsim?i want to work with modlesim, and try it,,, do u know to create this test bench for modlesim, is there automatic way
You can also refer to the following user guide to create stimulus waveform using modelsim waveform editor.
http://www.altera.com/literature/ug/ug_gs_msa_qii.pdf?gsa_pos=19&wt.oss_r=1&wt.oss=waveform editor For a design with complicated simulation, I would recommend you to create a testbench.