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Altera_Forum's avatar
Altera_Forum
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11 years ago

Modelsim "Types do not match"

Hi, I've wrote VHDL code, and also a testbench. Its my first attempt writing testbench so go easy please. I think it's correct but Modelsim keeps giving errors; I have tried numerous times with no jo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

hi.

In entity quarter_round you declared port y as unsigned. When you declared the component in the testbench, you declared the port as std_logic_vector. Usually the entity ports are of type std_logic or std_logic_vector.