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Honored Contributor
Honored ContributorModelSim "True Dual Port" Memory viewer weird
Hi everyone. I have a question for you all. I have a FPGA VHDL design using Cyclone III, in my design I used internal memory configured as true dual port RAM. I created the VHDL code, simu...
Altera_ForumHonored Contributor
Honored ContributorI've not maybe understood the problem.
You told: "I write data into Port B, after writing sequence finished then I read data inside memory from Port A. So I don't read data being written in the same time." and before "I can see the content of memory from Port A" that is right since you're writing data on port B and reading from port A. Moreover there is no problem at all as you've stated.. What do you mean when you tell "when I tried open window form Port B"? What are you using for simulate it? Internal Quartus II simulator that is present until v9.1 or maybe Simulink with a vhdl/verilog testbench?
