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Hello guys,
I have some issues when trying to set-up the input signal of a vhdl design in transcript.
From what I have undestand, supposing that my input signal is
/d
, if I want the signal to have a change of 10 every 100 ns I should write :
vsim> force -deposit /d 10#0, 10#10 100, 10#30 100, 10#40 100
By the way, when I run the model (run 500) I see that the
/d
waveform has a value of 0 at 0 ns, changes to 40 at 100 ns and then remains at 40.
What am I missing ??
Thank you for any suggestions.
Have a nice day.
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The time goes in absolute mode. So it has to be rewritten as:
vsim> force -deposit /d 10#0, 10#10 100, 10#30 200, 10#40 300
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