Modelsim starting vsim with out typing the additional -L <library> each time

Hi,

Are you using the Intel FPGA Edition of ModelSim or a standalone edition? If using the Intel FPGA edition, the device libraries should already be precompiled for the simulator and you can see them in the libraries list.

If using a standalone version, you will need to compile the device libraries for the simulator via Quartus -> Tools- > FPGA Library compiler. Select the simulator , specify the path to the simulator and then choose the device family and compile. This will create the device specific libraries for ModelSim.

To simulate the designs, you will need to specify the libraries using the -L option. The other way around is to compile the required device libraries into your designs work folder and then simulate. This way the libraries and components are all available in the Work library and you need not specify the -L option.

Another option is to specify the libraries in the Modelsim.ini file that resides in your work library. Edit the file and add the following lines to it:

; Altera Primitive libraries

;

; VHDL Section

;

altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf

altera = $MODEL_TECH/../altera/vhdl/altera

altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim

lpm = $MODEL_TECH/../altera/vhdl/220model

220model = $MODEL_TECH/../altera/vhdl/220model

maxii = $MODEL_TECH/../altera/vhdl/maxii

maxv = $MODEL_TECH/../altera/vhdl/maxv

fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm

sgate = $MODEL_TECH/../altera/vhdl/sgate

arriaii = $MODEL_TECH/../altera/vhdl/arriaii

arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi

arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip

arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz

arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi

arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip

stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv

stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi

stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip

cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv

cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi

cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip

cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive

stratixv = $MODEL_TECH/../altera/vhdl/stratixv

stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi

stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip

arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz

arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi

arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip

arriav = $MODEL_TECH/../altera/vhdl/arriav

cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev

twentynm = $MODEL_TECH/../altera/vhdl/twentynm

twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi

twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip

cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp

;

; Verilog Section

;

altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf

altera_ver = $MODEL_TECH/../altera/verilog/altera

altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim

lpm_ver = $MODEL_TECH/../altera/verilog/220model

220model_ver = $MODEL_TECH/../altera/verilog/220model

maxii_ver = $MODEL_TECH/../altera/verilog/maxii

maxv_ver = $MODEL_TECH/../altera/verilog/maxv

fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm

sgate_ver = $MODEL_TECH/../altera/verilog/sgate

arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii

arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi

arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip

arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz

arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi

arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip

stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv

stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi

stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip

stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv

stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi

stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip

arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz

arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi

arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip

arriav_ver = $MODEL_TECH/../altera/verilog/arriav

arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi

arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip

cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev

cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi

cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip

cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv

cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi

cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip

cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive

twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm

twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi

twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip

cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp

Hi,

Thanks for the info. I use standalone modelsim, but I just compile the quartus/eda/sim_lib/ sources directly from modelsim.

I suspect your right that the ini file will allow this because I have a testbench from somebody else and it allows starting vsim without having to type -L option and its in the [Library] section which mentor docs says will allow not having to type this in for commmon libraries, but when I cant seem to duplicate this in my own project.

I tried adding the altera_mf_ver library to modelsim.ini also the project.mpf file but I still have to type -L altera_mf_ver. Is there a way to tell what libraries are default loaded and runtime? This would help debug if its a modelsim.ini sytax read error or something else.