Forum Discussion
EEren
Occasional Contributor
Occasional ContributorModelsim is not simulating.
I have a module I want to test
out_control.vhd
entity OUT_CONTROL is
port
(
CLK : in std_logic;
RST : in std_logic;
OUT_MASK : in std_logic_vector(55 downto 0);
OUT_ON_O...
EErenOccasional Contributor
Occasional ContributorWho is talking about Verilog ???!!!
Where do you see a single line of Verilog in my code ???!!!
Jesus Christ!!! Unbelievable!!!
