Forum Discussion
EEren
Occasional Contributor
Occasional ContributorModelsim is not simulating.
I have a module I want to test
out_control.vhd
entity OUT_CONTROL is
port
(
CLK : in std_logic;
RST : in std_logic;
OUT_MASK : in std_logic_vector(55 downto 0);
OUT_ON_O...
sstrell
Super Contributor
Super Contributorwait until doesn't exist in Verilog. Quick Google search for a replacement:
https://stackoverflow.com/questions/12370324/verilog-equivalent-of-wait-until-for
