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EEren's avatar
EEren
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Modelsim is not simulating.

I have a module I want to test out_control.vhd entity OUT_CONTROL is port ( CLK : in std_logic; RST : in std_logic; OUT_MASK : in std_logic_vector(55 downto 0); OUT_ON_O...
YEan's avatar
YEan
Icon for Contributor rankContributor
4 years ago

Hi there,

Do you have any update on your problem?

Thank you

Regards,

Ean

EEren's avatar
EEren
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Well...Some problems I resolved another pop up.

For example

process 
begin
    reset <= '1';
    wait for 100 ns;
    reset <= '0';

    wait until s_send_rdy = '1';
    s_send_data <= X"88";
    s_send_trig <= '1';
    wait for 40 ns;
    s_send_trig <= '0';
    wait until s_send_rdy = '0';

    wait until s_send_rdy = '1';
    s_send_data <= X"ED";
    s_send_trig <= '1';
    wait for 40 ns;
    s_send_trig <= '0';
    wait until s_send_rdy = '0';

    wait;
end process;

And I see

Is wait until working directive?

 

  • YEan's avatar
    YEan
    Icon for Contributor rankContributor
    4 years ago

    What does that mean working directive?