ModelSim Error

Mr. Moderator,

I am having the exact same error. Please find below the code I used this time. One thing, I want to mention here is that I have been using Quartus Prime Standard edition for last 4/5 years ( Got the license from Altera as a donation). I used only the verilog code to generate the VWF form without any issue until recently. It's really frustrating......

// define a module for the design
module mux21(in1, in2, select, out);

// define input port
input in1, in2, select;

// define the output port
output out;

// assign one of the inputs to the output based upon select line input
assign out = select ? in2 : in1;
endmodule

module test;
reg in1, in2, select;
wire out;

// design under test
mux21 mux(.in1(in1), .in2(in2),
.select(select), .out(out));

// list the input to the design
initial begin in1=1'b0;in2=1'b0;select=1'b0;
#2 in1=1'b1;
#2 select=1'b1;
#2 in2=1'b1;
#2 $stop();
end

// monitor the output whenever any of the input changes
initial begin $monitor("time: =%0b","input1 =%0b","input2 =%0b","select =%0b", "output =%0b", $time, in1,in2,select,out);
end
endmodule