Hi,
"I have a code which compiles correctly but when I simulate it using ModelSim, it gives me this warning:"
code which provided is not as per proper syntax especially library & architecture but I assume that, you could have compiled it correctly since you mentioned it. please refer the attached VHDL language reference manual for proper syntax.
if you compiled design(DUT) successfully then initialize all the inputs & outputs in test bench, the warning which you got it`s might be because of not initialization of Inputs& outputs.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards
Vikas Jathar
(This message was posted on behalf of Intel Corporation)