Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

modelsim Error: (vlog-13036) near "--": Operator only allowed in SystemVerilog.

Hi, After trying to simulate (with no success for now) Arria10 fifo with Quartus 18 Standard installation and modelsim altera starter edition in linux: https://www.alteraforum.com/forum/showthr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

you're compiling a VHDL file using the verilog compiler (vlog). You need to use vcom to compile VHDL files.