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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

I created own simple design file relative to the .vt file, refer the attached files & try yourself with fresh new project in Quartus tool.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)