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Altera_Forum
Honored Contributor
Honored Contributormodelsim does not generate clock signal
Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_ForumHonored Contributor
Honored ContributorNothing helps me :c
Maybe smth broken in Native link connetion. But when I intentionally made mistake in .vt file, Modelsim reported me about it so it sees and updates it during RTL simulation. You seemed to simulate this project without Quartus, how?
