Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Nothing helps me :c

Maybe smth broken in Native link connetion. But when I intentionally made mistake in .vt file, Modelsim reported me about it so it sees and updates it during RTL simulation.

You seemed to simulate this project without Quartus, how?