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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Yes, It should be "clk_clk".

Refer attached testbench file & run for more time like "run 50 ms".

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)