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Altera_Forum's avatar
Altera_Forum
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7 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

I replaced but still getting those strange pictures. I am sorry, but clock_period is a parameter (constant) how you made it posedge? Could you please provide me with your testbench file?

Thank you for your attention!