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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Replace sysclk by sysclk_period

It`s simple just provide input stimulus for example as follows & simulate, 

always @(posedge SYSCLK_PERIOD) begin
# 5 reset_reset_n = 1;
# 50 reset_reset_n = 0;
# 100 reset_reset_n = 1;
# 25 reset_reset_n = 0;
# 55 reset_reset_n = 1;
end

find the attachment for screenshot.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)