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Altera_Forum
Honored Contributor
Honored Contributormodelsim clock network stuck StX (gate level sim)
Hi All, I'm hoping someone can help with an issue I've observed in modelsim (10.5b, quartus 17.0). Simply put the clock network correctly drives the network right up to the point where it ...
Altera_ForumHonored Contributor
Honored ContributorHi,
I just simulated the code you posted. I did parse the code through Quartus and generate the netlist via the Netlist writer. The gate-sim works fine. I don't see any issues.https://alteraforum.com/forum/attachment.php?attachmentid=14499&stc=1
