Modelsim and CycloneV PLL : flat output

Hello everyone,

I am trying to simulate a QSys design with Nios and custom IPs, one of them including a reconfigurable pll.

I am able to compile my design, simulate it, but when simulating, clock outputs from the pll stay at a value of '0' and it doesn't lock.

What makes it tricky is that I can simulate the IP which contains the PLL with a testbench and everything works fine. but when this IP is placed in a wider qsys design it doesn't work.

I watched pll inputs ant outputs, nothing seems suspect except its flat outputs :

pll startup :

https://www.alteraforum.com/forum/attachment.php?attachmentid=8865

as you can see, output clocks stay flat, but reconfig_from_pll has a legit value.

the libraries I use in my design :

    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                       -work altera_ver           
    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                                -work lpm_ver              
    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                   -work sgate_ver            
    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                               -work altera_mf_ver        
    vlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"           -work altera_lnsim_ver 
    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                          -work cyclonev_ver    
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"                 -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"             -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"                -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"             -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"          -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"                     -work altera               
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                               -work lpm                  
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                              -work lpm                  
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                            -work sgate                
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                                 -work sgate                
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"                  -work altera_mf            
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                             -work altera_mf            
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"               -work altera_lnsim         
    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"            -work cyclonev        
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"                        -work cyclonev             
    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"                   -work cyclonev

they are all given as -L arguments to the vsim command.

the pll simulation file I use :

  vcom     "D:/dev/TstPtfm/output_files/testbench/TstPtfm_tb/simulation/submodules/altera_pll_clock_gen.vho"              -work clock_generator

when vsim loads the component :

#  Loading clock_generator.clock_def_pkg(body)#  Loading clock_generator.f_clock_generator_ip(imp)#  Loading altera_lnsim.altera_lnsim_components#  Loading clock_generator.altera_pll_clock_gen(rtl)#  Loading sv_std.std#  Loading cyclonev_ver.cyclonev_lcell_comb#  Loading ieee.vital_timing(body)#  Loading ieee.vital_primitives(body)#  Loading cyclonev.cyclonev_atom_pack(body)#  Loading cyclonev.cyclonev_components#  Loading sgate.sgate_pack(body)#  Loading clock_generator.altera_pll_reconfig_clock_gen(rtl)

it seems that all necessary libraries are loaded.

I already RTFM and googled my problem. The only thread that could be related is :

http://www.alteraforum.com/forum/showthread.php?t=42356&referrerid=90168

I already had to deal with this "error in protected content" issue and used the solution given in the thread (include verilog lib).

My question is simple : do you have any idea of what is happening and how to solve it?

Thank you for reading all this and have a good day!