Honored Contributor
Honored ContributorHi Joe:
I don't believe so. I didn't see any thing about it. It just removes the 10k line limit, but still has a 3k instantiation limit from what I can see.. And based on their metrics is a little faster the ASE. http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html?gsa_pos=3&wt.oss_r=1&wt.oss=modelsim-altera%20edition I know coverage use to be an add-on for Mentor SE/PE, but with DE they threw it in. All seem to have some system verilog support, but for full assertion support, you pretty much need either and add-on license, or higher end version. They are all too expensive, in my humble opinion, and I hate how they nickle and dime you on features. AE wasn't really an option for us, since we need to do both Altera and Xilinx designs depending on our customers. Pete
