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Altera_Forum
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11 years ago

ModelSim-Altera Problem with PLL IP Core

I have some simple VHDL code. One file has an UNSIGNED counter: signal count : unsigned(3 downto 0); The TOP level entity has the clock as input. If I use this clock for the counter which is an in...
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Altera_Forum
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11 years ago

Found the problem.

My code uses a "synchronous" reset. If one uses a reset on the PLL then all clocks are stopped during the reset.

Thus, no reset code will be executed.!

Solution: Permanently tie PLL reset to GND.