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Altera_Forum
Honored Contributor
10 years agomodelsim-Altera "create wave" problem with generic
I am using Quartus Prime Lite 15.1/modelsim-Altera starter 10.4 - university edition (professor) When I create fixed ports in VHDL ... port (aa, bb: in STD_LOGIC_VECT...
Altera_Forum
Honored Contributor
10 years agoThe design was properly elaborated - no errors or warnings. I've attached a screenshot of modelsim showing the incorrectly generated "create wave" signals AND the correctly generated simulation variables. Again - this works fine if I remove the Generic form the code and replace it with a constant.
https://www.alteraforum.com/forum/attachment.php?attachmentid=12332