ModelSim Altera 6.1g

You can look at some design examples at

http://www/support/examples/modelsim/exm-modelsim.html

The above examples are for gate level simulations.

Further you can find some more details for ModelSim Altera at http://www/support/software/quartus2/simulation/sof-qts-simulation.html

-Lakhat

romaprince, I found it very useful to download dsgn_msim_ae_ver.zip from the following Altera.com website: http://www.altera.com/support/examples/modelsim/exm-timing-verilog-msaltera.html.

If you unzip the folder, you will find a file called multiplier_run_msim_gate_verilog.do (which resides in the /modelsim directory). The *.do file show's the command line of how to compile, load the simulation, and add/view/run wave in the Modelsim-Altera simulator.

If you are still receiving a specific error or warning message, please let me the exact steps which lead up to the error/warning. Additionally, please let me know the exact error or warning message and I can try to assist. :)

From Hassien: i cant start ModelSim Altera 6.1g

Reply: Hi Hassien, do you mean you can't open Modelsim Altera 6.1g? When you double-clicked the Modelsim Altera 6.1g, any fatal errors displayed out? From my experience, if you can't open Modelsim Altera 6.1g, there is due to License issue. First you need to confirm the version of your Modelsim Altera suit to your Quartus Version.

From romaprince: I used ModelSim Altera 6.1g to simulate my designs, i have walked through all steps introducted from user's guide but when i performed Add ~~~> wave to a selected signal in order to test its results in ModelSim enviroment simulation, i couldn't load my designs into ModelSim libraries.

Reply: If you are using command line to perform your simulation, I would like to introduce you the template below:

vlib work

vmap work work

vlog -vlog01compat -work work <all your files>

vsim -t 1ps +transport_int_delays +transport_path_delays -l <lib_name1> -l <lib_name2> -l work -voptargs="+acc" <your test bench module name>

add wave *

view structure

view signals

run 1000 ns

Please note that the command of add wave * is to only add all your testbench input and output signals. If you wish to view other signals, from the hierarchy, find out the instance name which is instantiating the ports from your testbench toward your top-level module, then you may extend the hierarchy to find out the modules which you wish to debug in Modelsim. Select the module and you can observe all the ports of this selected module at the "Object Plane" , you can drag any signals you wish to debug from the "Object Plane" to the Waveform and run your design. Advance information for you, after you retrieve out all the signals that you wish to debug, you can save the setting into a file named as wave.do file, this is to ease you when you wish to debug in future, you no need to find out all the signals again.