Forum Discussion

SteveRiley's avatar
SteveRiley
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Modelsim - greybox netlist file

I followed the quick start guide and the example project (ModelSim* - Intel® FPGA Edition Simulation Quick-Start) and it work fine as outlined. Using this as a template on a different project, the ...
  • SteveRiley's avatar
    SteveRiley
    4 years ago

    In the above, I did not regenerate the library (launching the simulation library compiler). After doing so, the correct path names were present and the simulator was properly launched. Now that I have Modelsim running, I need to figure out why the generated IP's simulation files are not working. Example is a simple PLL, where the clock out is not toggling.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

You mean like ClockPLL.v? That's a top-level file for the IP generated when you create the IP using the IP Catalog in Quartus. That becomes part of your design.

SteveRiley's avatar
SteveRiley
Icon for New Contributor rankNew Contributor
4 years ago

Yes.

The IP files (list above excluding the test bench and top level design).

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Yeah, the IP Parameter Editor creates those after you parameterize an IP.

    • SteveRiley's avatar
      SteveRiley
      Icon for New Contributor rankNew Contributor
      4 years ago

      I am using 20.4 and those files are not being generated.

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        So you're creating IP from the IP Catalog, generating the code for them (Generate HDL button in the parameter editor), and you're not getting the files generated? If not, there is something very wrong with your Quartus installation.