Forum Discussion
SteveRiley
New Contributor
New ContributorModelsim - greybox netlist file
I followed the quick start guide and the example project (ModelSim* - Intel® FPGA Edition Simulation Quick-Start) and it work fine as outlined. Using this as a template on a different project, the ...
In the above, I did not regenerate the library (launching the simulation library compiler). After doing so, the correct path names were present and the simulator was properly launched. Now that I have Modelsim running, I need to figure out why the generated IP's simulation files are not working. Example is a simple PLL, where the clock out is not toggling.
sstrell
Super Contributor
Super ContributorYou mean like ClockPLL.v? That's a top-level file for the IP generated when you create the IP using the IP Catalog in Quartus. That becomes part of your design.
SteveRileyYes.
The IP files (list above excluding the test bench and top level design).
- sstrell
Yeah, the IP Parameter Editor creates those after you parameterize an IP.
- SteveRiley
I am using 20.4 and those files are not being generated.
