Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI have seen the user guide from MOdelSim user manual , there's a "grouping files" function.
explanation from the user manual : you can group two or more files in the compile order dialog so they are sent to the compiler at
the same time. for example, you might have one file with a bunch of verilog define statements
and a second file that is a verilog module. you would want to compile these two files together. I have grouped the ddr_par.v a .v file and compile them together , but I got 1 error message : no compile information available. the source file may have been edited and saved since the last compile. I am new to ModelSim, so I'm hoping for your the advice. Thank you, Yuyex:o