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Altera_Forum
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11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
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Altera_Forum
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9 years ago

If you maintained the communication between the channel and the host outside of the OpenCL infrastructure that should be possible. As long as the channel is exposed in the BSP as a Avalon-ST interface then the kernel should be able to communicate with it but that means it's up to you to take care of the other side of the channel yourself. This could get very messy though if that side band information needs to stay synchronized with kernel invocations so before going too far down that road I would try to determine if you really need to do this.