Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

I have a related question. Is it possible to have a channel communicate with OpenCL directly. What i am looking at is to have a channel defined in the BSP which i can write to from a C/C++ host application and have the OpenCL kernel read from the channel as an I/O channel. It seems related to what popoolab wanted to do, but the difference is that i want the host-program to talk via a channel instead of a Verilog component.

Any pointers would be appreciated.

Thanks!