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Altera_Forum
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11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Wow, lucky me then! Enjoy your vacation ;)

Thanks, I'll dig on the references in the link you provided and see what'll come. The SoCKit BSP I'm using is the one on RocketBoards, and is targeted to 14.0 version, but works fine with 15. I'll also try to find if there is a newer version, as it is stated that the 1GB memory on the FPGA side was not available in the BSP, but it would be added on future releases.