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Altera_Forum
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11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
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Altera_Forum
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9 years ago

Caught me right before my long vacation :) Actually I haven't worked on OpenCL in quite a while so I'm not sure what the official flow is anymore. I suspect 15.0 is fine but you might find that 15.1 has improved support. Going by memory there is an .xml file that goes with the BSP that describes the various MM and ST connections within the BSP and so it would be a matter of adding your streaming IP into the Qsys system and including it in the BSP. I suspect that this stuff should be documented by now so I would start on this page: https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html

If you are targeting an SoC then I recommend using the SoC "platform" as the starting point. Luckily SoC BSPs are much easier to build since you typically do not have PCIe and DMAs and instead just provide the HPS SDRAM slave port to the BSP so that kernels can connect up to it. Chances are you can take the SoC platform and just pin it out for your board and it should be fairly seamless. Then I would add the streaming IP to the BSP once you are satisfied that the port was successful.