Mixing OpenCL kernel with VHDL Netlists

Hi, BadOmen, have you made any progress in this subject recently? I have a custom module that I'd like to try to integrate with an OpenCL kernel ir order to let it manage the datapaths, rather than caring for it myself. I'm using an Arrow SoCKit board with Quartus 15.0.

I'd specially like to know what exact xml file is needed to be modified and where I can find documentation about BSPs. In the future, we're planning to design a custom board with a Cyclone/Arria SoC, then we'll have to create our own BSP.

Thanks in advance.