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Altera_Forum
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11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_Forum's avatar
Altera_Forum
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10 years ago

My email bounced back so I'll just describe what I did. First I made a copy of the BSP for the board and pointed my environment to use it instead of the one that came for the board. I then opened the Qsys design and added my custom IP to it. Then I edited the board .xml file to add my custom IP to it by describing it's interface (Avalon-ST source). In my kernel I referenced the channel using the same name as what I defined the name to be in the .xml file.

This stuff should be documented fairly well in the OpenCL documentation so I would take a look at it. To test it I recommend generating to the intermediate file (.aoco) then in the generated files open the Qsys system to see if your kernel got stitched up to the custom hardware correctly.