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Altera_Forum
Honored Contributor
Honored ContributorMixing OpenCL kernel with VHDL Netlists
Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_ForumHonored Contributor
Honored ContributorYes, I see the point of using channels and the simply kernel as you have described it, as it means it would limit the movement of data between the FPGA and the host. I will explore both avenues. Also, I have sent you a private message.
Cheers
