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Altera_Forum
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11 years ago

Mixing OpenCL kernel with VHDL Netlists

Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes, I see the point of using channels and the simply kernel as you have described it, as it means it would limit the movement of data between the FPGA and the host. I will explore both avenues. Also, I have sent you a private message.

Cheers