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Altera_Forum
Honored Contributor
Honored ContributorMixing OpenCL kernel with VHDL Netlists
Hi, Is it possible for the output of an OpenCL kernel to reside in the same FPGA as a VHDL netlist? For example, could I implement an algorithm in OpenCL and a display driver in VHDL? The intentio...
Altera_ForumHonored Contributor
Honored ContributorI don't think it is possible : the aoc compiler translates your OpenCL kernel to a VHDL/Verilog project, and generates all the files that are needed to build the final bitstream. I doubt editing the VHDL/Verilog by hand is doable !
