Honored Contributor
Honored Contributor“they will usually specify the templates they accept for various hardware elements in their documentation (Quartus does).”
“Verilog is defined as a language with bahavioural features” According to this, does it in any way suggest that there is NO LOWER/UNDERLYING standard for how verilog is synthesized, which is probably understandable since companies might implement proprietary gate/logic units. I wonder if there had been any attempt to standardize synthesizer implementation, or perhaps all unsuccessful because this is close to physical level so it might change as device technology advances?
