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Altera_Forum's avatar
Altera_Forum
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14 years ago

Missing STH Instruction

Hey Guys,

I have a problem concerning a communication between a 32 Bit Avalon Master and the 16-Bit UART Avalon Slave.

My processors data width is like the address width 32 Bit. But I don't have a "Store halfword" Instruction but a "Store Word" and "Store byte" Instruction.

Using my StoreWordInstruction all my ByteEnable are 0b1111 and using my StoreByteInstruction(STB) 0b0001 / 0b0010 / 0b0100 / 0b1000.

If I perform an STB to the Control Register to my Uart the Avalon Fabric always fills the remaining 8 Bits with Zeros. So the problem is that when I perform 2 consecutive STB's to write the 16Bit Control Register, the Fabric performs two 16-Bit writes and the first overwrites the second one.

I hope you can uunderstand it. Thanks a lot so far.

Michael

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Unfortunately the UART in SOPC Builder/Qsys doesn't have byte enables otherwise what you are attempting would be perfectly fine. Any time a master accesses a slave like this (native slave) the fabric treats the access as an atomic operation which is why you are seeing zeros written in.

    If you perform a 32-bit write then the lower 16-bits will be passed in and the upper 16-bits will be dropped. So are the word accesses causing problems as well?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the reply.

    In fact, the word access doesn't cause any problem as it seems. But isn't youre statement conflicting with the Interface Spec. in the Avalon Datasheet on page 3-16( http://www.altera.com/literature/manual/mnl_avalon_spec.pdf )?

    "If the master is wider than the slave, data bytes in the master address space map to multiple locations in the slave address space. For example, when a 32-bit master port performs a full 32-bit read transfer from a 16-bit slave port, the interconnect executes two read transfers on the slave side on consecutive addresses,..."
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    HEy Guys.

    My Uart Tx works now perfectly, even with interrupt generation.

    But if I try to send data to my Uart, so testing the Rx, there is absolutely no function. Neither in Synthesis nor in simulation. There is no Interrupt Generation, nothing. And yes, I have enabled it in the control-register (content: 0b0000011000000).

    Any idea?

    Thanks so far.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The spec is written around dynamic addressing (slaves with byte enables) since native addressing is depricated. In Qsys however a wide master accessing a narrow native slave will cause potentially multiple back to back accesses to occur. In SOPC Builder the upper bits were always lost so the fabrics behave a bit differently when it comes to native addressing. This is one of the many reasons why I recommend that anyone creating a new component with slave ports always include byte enables.