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Altera_Forum
Honored Contributor
14 years agomissing .sdc file...
hi all. i have this critical warning in my program during compilation.. the error says "Critical Warning (332012): Synopsys Design Constraints File file not found: 'xx.sdc'. A Synopsys ...
Altera_Forum
Honored Contributor
14 years agoPlease correct me if I'm wrong..
-Constraining the clock to,say, 20 ns means that any change in state less than that period is not "considered" as a clock signal? -And, constraining the input/output delay means that the delay is always in the range set in the sdc file? the range set is based on base clock of the input/output?