mismatched ports with Megafunction RAM

Hello,

I trying to implement a dual port RAM using a megafunction. Using Quartus, I can compile a simple RAM and a set of RAMs constructed in a single block, but when I use one of these blocks in a larger design, I get an error:

G primitive "memory_64k_by_8_MRAM:inst2|altsyncram:altsyncram_component|altsyncram_se02:auto_generated|ram_block1a7" has mismatched parameters for port Port A, Data In File: ../Higher_level_mem_Block2/db/altsyncram_se02.tdf Line: 44

36 SUBDESIGN altsyncram_se02

37 (

38 address_a[15..0] : input;

39 address_b[15..0] : input;

40 clock0 : input;

41 clocken0 : input;

42 data_a[7..0] : input;

43 data_b[7..0] : input;

44 q_a[7..0] : output;

45 q_b[7..0] : output;

46 wren_a : input;

47 wren_b : input;

48 )

Any clues as to why I'm getting this error. Thanks in advance with your help.