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Altera_Forum's avatar
Altera_Forum
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12 years ago

Migration of Qsys PCIe IP Core from 13.0SP1 to 13.1 failed

Hello all,

It seems that migration of my PCIe IP from 13.0SP1 to 13.1 failed. Specifically, I'm getting this error: 

Info (12128): Elaborating entity "altpciexpav_stif_a2p_vartrans" for hierarchy "de2i150_core:u0|de2i150_core_pcie_hard_ip_0:pcie_hard_ip_0|altpcie_hip_pipen1b_qsys:pcie_internal_hip|altpciexpav_stif_app:avalon_stream_hip_qsys.avalon_bridge|altpciexpav_stif_tx:tx|altpciexpav_stif_a2p_addrtrans:a2p_addr_trans|altpciexpav_stif_a2p_vartrans:vartrans"Error (10198): Verilog HDL error at altpciexpav_stif_a2p_vartrans.v(121): part-select direction is opposite from prefix index direction
Error (10784): HDL error at altpciexpav_stif_a2p_vartrans.v(52): see declaration for object "PbaAddress_i"
Error (12152): Can't elaborate user hierarchy "de2i150_core:u0|de2i150_core_pcie_hard_ip_0:pcie_hard_ip_0|altpcie_hip_pipen1b_qsys:pcie_internal_hip|altpciexpav_stif_app:avalon_stream_hip_qsys.avalon_bridge|altpciexpav_stif_tx:tx|altpciexpav_stif_a2p_addrtrans:a2p_addr_trans|altpciexpav_stif_a2p_vartrans:vartrans"
Info (144001): Generated suppressed messages file ...
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 124 warnings
    Error: Peak virtual memory: 789 megabytes
    Error: Processing ended: Sat Nov 16 15:48:15 2013
    Error: Elapsed time: 00:00:31
    Error: Total CPU time (on all processors): 00:00:42
Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 124 warnings

And I'm curious why this happens. I'm by no means an expert on PCIe or Verilog.

I have included the file.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    I get the same exact same error. I'm guessing you are also configuring the PCI core with Fixed translation table, and one address page for the address translation?

    If I change the setting to two address pages, it is possible to compile without error. This is not the setting I need in my design.

    The error is inside the file altpciexpav_stif_a2p_vartrans.v

    However, the in the file altpciexpav_stif_a2p_addrtrans, which instantiates altpciexpav_stif_a2p_vartrans, it will select altpciexpav_stif_a2p_fixtrans instead, if CB_A2P_ADDR_MAP_IS_FIXED is set.

    When I trace the parameter CB_A2P_ADDR_MAP_IS_FIXED in the modules I can see that this is never true:

    On the top_level of the pcie_core parameter CB_A2P_ADDR_MAP_IS_FIXED is set to 1 when I have selected fixed translation table.

    Further down in the module altpciexpav_stif_app the parameter setting CB_A2P_ADDR_MAP_IS_FIXED is suddenly hardcoded to 0.

    So when reaching the module altpciexpav_stif_a2p_addrtrans the setting is always 0.

    I don't know if this is a bug, or done on purpose to always use altpciexpav_stif_a2p_vartrans instead of altpciexpav_stif_a2p_fixtrans...

    I tested setting changing the code such that CB_A2P_ADDR_MAP_IS_FIXED was passed further down, but my design did not work. (The same design works when I generate and compile with Quartus 12.1 sp1, I have not tested with 13.0).

    So it seems that the hardcoding was done on purpose to always use the altpciexpav_stif_a2p_vartrans module, but this module does not support just one address page for the address translation (yet)...

    Best Regards,

    Jon