Migrating Xilinx Coregen files to Altera as EDIF Netlists

I doubt you can import EDIF netlists unless they are contain purely logic.

I vaguely recall that when I used Mentor Precision RTL to target Altera devices, the Altera LPM components were passed through the EDIF netlist as 'black box' components. I wouldn't be surprised if the Xilinx tools did something similar.

What you should do instead is create a testbench that verifies the functionality of your Xilinx based design, and then incrementally replace the Xilinx components with Altera components. I've used Modelsim Altera Starter Edition to compile Xilinx designs. You just have to compile the library components. Once you've converted the design to Altera components, then you can simply synthesize it directly from the source, rather than an EDIF netlist.

Cheers,

Dave