--- Quote Start ---
I don't recall that they were called ALTSYNCRAM in the MegaWizard. I thought they were called "RAM: 1-port", "RAM: 2-port" etc in the GUI.
The ALTSYNCRAM components are fairly easy to instantiate directly in VHDL/Verilog. Just use the MegaWizard to create a couple of instances of RAM to get an idea of how the generics/parameters change, and then create your own instance. I prefer to use this method, as I can leave the RAM size generics as generics.
Cheers,
Dave
--- Quote End ---
Thanks Dave.
9.1 does indeed support ALTSYNCRAM in the Megawizard, but, in the V11+ gui, Altera seems to have deprecated ALTSYNCRAM in favor of "RAM: <1|2>-port". The module is the same, but for some reason the names have changed.
I'd be happy to instantiate in Verilog, but the design was originally done in bdf with tdf files *cough*. For the sake of others on the project who are used to schematic capture insanity, I'd like to keep the design maintainable through the current workflow. Unfortunately, The design has about 40 unique ALTSYNCRAM components. I know one path is to regen each one as a "RAM: <1|2>-port" type component, but I was hoping there was a more automated way to handle this. This seems simply a case of semantic support in the Altera GUI, the command line still references an "altsyncram" module. I was hoping I'm not the only person that has run across this problem.
My fall back is likely to go with HDL wrappers that allow changing of the settings textually. Unfortunately, it appears my only option here seems to be tdf or VHDL - the 9.1 doesn't appear capable of generating Verilog wrappers for the components.
Honored Contributor
