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Altera_Forum
Honored Contributor
Honored ContributorMeeting timing requirements with async signal.
Hey everyone. I've been studying computer architecture for some time, but I'm still new to circuit design and VHDL, so this might be obvious, but I still need help. I'm developing a MIPS style p...
Altera_ForumHonored Contributor
Honored ContributorNot many pointers to your problem. The code does look like large mux but should not by itself be the problem in modern FPGAs.
Your problem seems outside and my suspicion is on clock and its inversion? and you also title your post with async? you need to describe why and how you invert clock and what is this async to do with timing.