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I don't think that it's too much for a compiler to verify, VHDL e.g. accepts similar expressions where both range limits are calculated. I believe that those people who designed Verilog tried to avoid unnecessary compiler effort with the explicite indexed part-select syntax.
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It is one thing to be able to calculate indexes at runtime using actual values, but it still much more complex to calculate the width symbolically at compile time. VHDL treats logic vectors as strings with resolution functions for all operators that get called at runtime. Verilog, on the other hand, with all of its implicit type conversions does all of this resolution at compile time. This helps Verilog calculate expressions faster than VHDL.
SystemVerilog allows you to use the streaming operator where the width does not need to be constant.
d <= {<<{b with [a:a-2}};
The bits of b that are assigned to d are calculated at run time.
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